32-bit paging: CR0.PG = 1 & CR4.PAE = 0 (section 4.3) CR0.WP CR4.PSE CR4.PGE CR4.SMEP CR4.SMAP PAE paging; CR0.PG = 1 & CR4.PAE = 1 & IA32_EFER.LME = 0 (section 4.4) CR0.WP CR4.PGE CR4.SMEP … 閱讀全文 Intel 64 and IA32 architectures Memory Model – Segmentation and Paging